With the evolving of semiconductor technologies, semiconductor dies are becoming increasingly smaller and thinner. As a result, the packaging of the semiconductor dies becomes more difficult, adversely affecting the yield.
Package technologies can be divided into two categories. One category of packaging is referred to as chip level packaging, in which dies are sawed from wafers before they are packaged. Advantageously, only “known-good-dies” are packaged. Another advantageous feature of this packaging technology is the possibility of forming fan-out chip packages, which means that the I/O pads on a die can be redistributed to a greater area than the die, and hence the number of I/O pads packed on the surfaces of the dies can be increased.
The other category is typically referred to as wafer level package (WLP), in which dies on a wafer are typically packaged before they are sawed. The WLP technology has some advantages, such as greater throughput and lower cost. Further, less under-fill or molding compound is needed. However, WLP suffers drawbacks. Typically, wafer level packages are formed in a bare-die form as shown in FIG. 1. Solder balls 12 are formed on the top surface of die 10. After being sawed from the respective wafer, die 10 is not protected by any molding compound. Corners 14 of die 10 are thus subject to chipping. A further problem is that since increasingly more circuits and functions are packaged into a single die, the dies needs better heat dissipation ability. Such a requirement is not addressed by existing wafer level packaging processes. Accordingly, new packaging techniques are required.